There is a continuous demand for improved integrated circuits having higher performance and lower power consumption. Traditionally, the development of integrated circuits has to a large extent been relying on continuous downscaling of semiconductor structures, such as complementary metal oxide semiconductor (CMOS) devices. To push technology to even smaller dimensions, new device technologies, such as Fin Field Effect Transistor (FinFET) structures, have been introduced in the CMOS mainstream starting from the 14 nm node and below. The FinFET technology relies on a multi-gate transistor structure that offers performance improvements compared to existing planar CMOS devices. In a FinFET, the gate of the device is generally wrapped over the conducting source-drain channel. As a result, lower threshold voltages and better performance may be obtained and reductions in both leakage and dynamic power may also be achieved.
It may also be beneficial to replace the conventional Si-based source-drain channel with high mobility materials, such as Ge. Improved Ge-based pMOS channel performance has, for instance, been demonstrated with an intrinsic hole mobility being significantly larger than for Si and with an increase in device current. However, devices based on relaxed Ge may not out-perform the current state-of-the-art devices comprising strained Si. It is known to those skilled in the art that strain (e.g. uniaxial or biaxial) may be used to improve carrier mobility in microelectronics. This is of technical relevance, as an increase in channel mobility may result in advantages such as reduced electrical resistance, improved efficiency, increased current, and increased speed. Much attention is therefore directed towards developing strained Ge based devices.
Significant advances have been demonstrated in high mobility non-planar devices utilizing SiGe or Ge structures, but integration challenges still remain. It has for instance been identified that contamination and surface roughness at the interfaces within the devices are limiting the device performance. Hence, there is a need for improving surface quality in order to, for instance, reduce problems such as dislocation formation and surface roughness of the strained channel material. Consequently, there is a desire for better methods for forming nanoscale devices comprising strained semiconductor structures.